Digital hardware · Independent
32-bit Single-Cycle Processor
An ARMv4-subset processor with a complete single-cycle datapath and controller, simulated in ModelSim and demonstrated on a DE10-Lite FPGA.
- VHDL
- Quartus
- ModelSim
- MAX 10
Goal
Implement a 32-bit processor for a subset of the ARMv4 instruction set. The design connects fetch, decode, execute, memory, and writeback as functional stages within one cycle; it is not a pipelined processor.
My Role
I independently designed and implemented the processor datapath and controller in VHDL and Intel Quartus, working from supplied architecture diagrams, skeletons, and support modules. I also wrote assembly routines to exercise the design on a DE10-Lite FPGA.
How It Works
Provide the operands each instruction needs
The register file stores 16 × 32-bit words and has three read ports and one write port. The 32-bit ALU works with carry, overflow, negative, and zero flags.
Decode several immediate formats
I handled 8-, 12-, and 24-bit instruction fields using zero/sign extension, rotation, and branch-address calculation for arithmetic operands, memory offsets, and control flow.
Coordinate the datapath
A combinational controller generates 12 control outputs for operand selection, register and memory writes, flag updates, writeback, and conditional control flow.
Testing & Debugging
A 1–10 summation exposed a writeback bug: the accumulated value was not preserved across loop iterations. I traced the failure in ModelSim waveforms to the MOV register instruction’s WD4SEL entry in my controller spreadsheet. I replaced its don’t-care value with the ALU-result selection, updated the VHDL, and reran the simulation to verify the accumulated value on successive iterations.
Result
The processor-only MAX 10 design fitted using 2,713 logic elements. I demonstrated processor execution on the DE10-Lite hardware.